Ultimate VLSI Roadmap: Exploring Every Role in Chip Design
The Ultimate VLSI Roadmap is designed to help students and professionals gain clarity in choosing a role for their future careers.
Introduction
This blog is designed for students seeking a complete roadmap of chip design in the industry. While I won’t be teaching subjects here, if you have basic knowledge of VLSI and electronics, you can use this blog to gain clarity on the career path you should pursue. I will provide detailed insights into various job roles involved in chip design and fabrication, explaining the responsibilities of engineers at different stages. If you aspire to take on one of these roles, I will also give an in-depth explanation at an engineer's daily work, the tools they use, and the skills required to succeed in that role.
Lets start with some high level perspective of chip design roadmap and then I then i will dive into specifics of each role. There are companies that design the chips(Ex: Nvidia, Micron) and then there are companies that manufacture the chips(Ex: TSMC, Global Foundries) and then there are a few companies that that design and fabricate the chips(Ex: Intel, Samsung). Only a few companies can do both design and fabricate but they are actually good at either fabrication or design not both. Here I will give you in detail explanation of just the design roles I will not be explanation about the roles involved during fabrication of the chips.
Ok lets start with how or who decides how the capabilities of a chip(Ex: CPU, GPU). The chip architect typically decides an ASIC’s capabilities, guided by marketing and system-level requirements, Marketing determines market needs and goals, But these days it is the competition between the companies to be the leader in the chip industry, To be the best and have the fastest/reliable CPU and GPU, The world is moving towards AI adoption in every sector and jobs, and to accommodate this AI boom companies are building massive data centers to handle the AI traffic, Just in the year 2025 all the countries in total have agreed to spend 1.3 trillion dollars, to push AI infrastructure and train better models of LLM. So what that means for the chip industry is the world needs billions and billions of GPU in the next decades and will a continue to grow for a foreseeable future.
I believe we are at the dawn of the new era of semiconductor world that powers AI. Just like how industrial revolution made man power useless, The new AI era is trying to make human thinking useless, Now AI is trying to replace most of the simple/creative jobs. We will see silicon valleys popping up in every major country in the next decade. So if you are looking to build a career in chip design, you have made a good choice. You will have a bright and busy future. Semiconductor is the new oil of the world. Everyone needs semiconductor chips but one who controls the supply will become the superpower of the world.
Ok based on the goal the companies want to achieve, a chip architect decides on the some basic parameters on die area, power, temp, performance
Roadmap
These are the roles and individuals involved in designing advanced semiconductor chips
Chip architect
RTL design Engineer
RTL verification Engineer
Physical Design Engineer
DFT Engineer
Signoff/Tapeout Engineer
This does not mean only 6 people can design a chip from scratch, In the real world it involves hundreds of Engineers all closely working together to design the chip. There are also other roles like Pre-silicon validation engineers, Synthesis Engineer, Physical design verification engineer, Post-silicon validation, Characterization engineers, Firmware/Software integration engineers, Packaging engineers, Test engineers, Analog/Mixed-Signal Design Engineer, Product engineers and many more. Who are also involved in the design process, But I will give a detailed explanation only about the roles I have mentioned in the list, Since they are the main engineers who work on the most complex parts of the chip. I will try to explain the other roles in my second blog.
In this blog, I will provide a comprehensive overview of these six roles, delve into the skills required to pursue each career, and explore what their daily responsibilities might look like. Creating and Fabricate the modern CPU/GPU chips stands as one of the most intricate achievements in human ingenuity. The machinery involved in manufacturing the small node 2nm, 3nm and 5nm are some of the most complex machine ever build by human beings. It costs tens of billions to develop and hundreds of millions of dollars to build some of these machines.
Note: This blog focuses solely on the roles involved in designing a chip from RTL to Tapeout. The processes of fabrication and testing that involve hundreds of additional engineers may be discussed separately in a different blog series.
1. Chip Architect
Role : At the very top of the hierarchy, we have the Architect a pivotal figure in chip design. Think of them as the mastermind or planner of the entire process. They're the ones who set the benchmarks for power, performance, and overall goals for the chip. Essentially, they define the parameters, deciding the acceptable range for factors like area, power consumption, and performance. Guided by marketing and system-level requirements they are the bridge between the management and the engineering teams.
Architect works closely with RTL, Physical and verification teams to the goals are feasible and if it can be met under the timeline. They discuss on the trade offs in terms of power, performance, area, and cost making adjustments to the design as needed. They devise a blueprint of all the blocks and determine how these components should be seamlessly integrated. The Architect is involved and consulted throughout various stages of the chip design process. They also Analyze safety mechanism and hardware software STL (software test libraries) tradeoffs and functional safety architecture solutions, methodology, and certification
Day in the life of Architect :
Architects spend a significant portion of their time in meetings, discussing solution designs with engineering teams, feasibility with product managers and discuss project updates
Creating TRM : Technical Reference Manual, Documentation and reference models for verification team. Without these it would be difficult to coordinate between different teams.
Modify the design document and specifications and Working out the tradeoff's for different implementation decisions or iterations.
Conduct meeting between different teams of RTL, Physical Design and Verification teams to debug the any issue that may arise.
Skills Needed :
Technical Skills : Deep understanding of Computer Architecture, Architecture Modeling, Trade-off Analysis, Memory and Interfaces Implementation, ASIC/FPGA/SOC design and implementation, RISC/ARM architecture, Design flow, Digital and Analog Circuit Design
Soft Skills : Project Management, Communication Skills, Teamwork
Programming Languages : C , C++, Verilog, VHDL
How to become a Chip Architect : Most roles in this field demand at least 6+ years of industry experience and a Master's or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science. Becoming a Chip Architect right after graduation is exceptionally challenging. As this position sits at the top of the hierarchy, it requires substantial experience, a strong foundation in teamwork, and a track record of success to thrive in the role. For recent college graduates, aiming to become a Chip Architect within five years can be a realistic and ambitious goal.
You should focus on projects/thesis on actual architecture, try to publish in architecture conference like ISCA, MICRO, HPCA, ASPLOS. Read papers from those conferences to get an idea of the current state of research/industry. The best way to start is to apply for positions in performance modeling for a architectural team and start building your way up.
Since Power and Performance are at the core of design, Best way is to start there. You should do a few project about Power/Performance to get a clear idea on how your future work might be.
Note: Skills and requirement will change according to the company, But I have mentioned everything I have researched.
Pic Courtesy: Chip-Architect
2. RTL Design Engineer
Role : An RTL (Register Transfer Level) Design Engineer is a specialist responsible for translating the chip architect's high-level blueprint into a synthesizable RTL description using hardware description languages (HDLs). After the chip architect finalizes the high-level design, the RTL engineer breaks it down into manageable modules, writes and optimizes the code, and ensures the design meets performance, power, and timing requirements. They also collaborate with verification teams to develop testbenches and build simulations for validating the design.
In large projects, there may be anywhere from dozens to hundreds of RTL designers working simultaneously on different sections of the chip. Their role involves optimizing and preparing the RTL for synthesis, ensuring it can be converted into a gate-level design that adheres to timing requirements and resource constraints. This phase represents the initial stage where the chip begins to take form. Additionally, RTL designers have to work closely with verification and physical design teams to achieve timing closure and meet all design specifications. That being said, in smaller companies, a designer often takes on dual responsibilities, handling both design and verification tasks.
Day in the life of RTL Design Engineer :
RTL designers spend most of their time writing and debugging RTL code for specific modules and running simulations to verify that design.
They would Participate in daily meetings to discuss progress, issues, and coordinate with other teams, to ensure a seamless progression of the design through various stages, focusing on discussions around timing, power, and area optimizations.
Analyzing and resolving errors or warnings reported by their tools, while consulting with colleagues to determine whether specific violations can be waived. RTL coding primarily involves connecting and integrating signals between third-party IPs and certain in-house IPs, typically without direct involvement in high-priority internal modules.
Documenting every design decisions, code, and verification processes.
Skills Needed :
Technical Skills : EDA Tools (Synopsys, Cadence, Mentor Graphics), Design fundamentals, FPGA/ASIC design flow of simulation and synthesis, TCL scripting, Computer architecture, Static timing Analysis.
Programming Languages : Verilog, System Verilog, VHDL.
How to become a RTL Design Engineer : Most roles in this field demand a BS or Master's in Computer Engineering, Electrical Engineering with focus on Digital design and VLSI. With the necessary skills, it is entirely feasible to step into the role of an RTL Design Engineer immediately after graduating.
Students should gain hands on projects, internships, or research labs where you can write and simulate HDL code. Should have a decent exposure to industry EDA tools for Design and Verification. You should work on a few projects related to RTL design to gain a better understanding of whether this is the field you want to pursue.
Participate in competitions/workshops online/offline related to RTL design. With the right skills and projects, becoming an RTL Design Engineer is achievable. However, since this is a highly competitive industry, you need to excel to secure your place. Build a passion for RTL code.
Note: Skills and requirement will change according to the company, But I have mentioned everything I have researched.
3. RTL Verification Engineer
Role : An RTL Verification Design Engineer is responsible for ensuring that the Register Transfer Level (RTL) design of a chip functions as intended according to the architect’s blueprint. Their primary role is to verify that the RTL design meets specifications and operates correctly before proceeding to subsequent stages, such as synthesis or physical design. They create simulation environments and test benches to ensure a reliable design before advancing further in the chip design pipeline. They act as the bridge between the RTL Design Engineer and the Physical Design Engineer by analyzing simulation results, debugging issues, and verify fixes and validating that the RTL code functions correctly according to the design specifications, before it undergoes synthesis.
In large companies, the ratio of RTL Design Engineers to RTL Design Verification Engineers typically ranges from 1:2 to 1:3. This means there are often two to three verification engineers for every design engineer. The larger number of verification engineers highlights the effort needed to thoroughly test and validate complex designs to meet performance standards. Usually there will be a synthesis engineer who optimizes the RTL design into a gate-level netlist representation suitable for further design changes. Verification engineer makes sure the chip will perform reliably once fabricated, reducing the risk of costly post-silicon fixes.
Day in the life of RTL Design Verification Engineer :
RTL verification designers spend most of their time writing or updating testbenches in SystemVerilog or similar languages While using EDA tools to run simulations and verify the design under various scenarios.
They review requirements to create a verification plan with an emphasis on test cases linked to specific requirements, working on developing components like predictors or sequences for a UVM testbench. also running random regressions to analyze the results, and report any identified bugs to the designer. Once the issues are resolved, rerun the regression and proceed to verify other features.
They will participate in meetings to discuss these finding with their team and possible solutions.
Documenting every design decisions, testbench, and verification processes.
Skills Needed :
Technical Skills : Design fundamentals, Computer architecture, Verification methodologies, Scripting skills, EDA Tools (Synopsys VCS, Mentor Graphics, Cadence Xcelium), Python/Perl scripting, UVM, FPGA/ASIC design flow of simulation and synthesis.
Programming Languages : Verilog, SystemVerilog, Python, Perl
How to become a RTL Design verification Engineer : Most roles in this field demand a BS or Master's in Computer Engineering, Electrical Engineering with focus on Digital design and VLSI. With the necessary skills, it is entirely feasible to step into the role of an RTL Design Verification Engineer immediately after graduating.
Students should engage in hands-on projects and internships focused on writing and simulating Verilog/SystemVerilog code, as well as applying verification methodologies. Having exposure to Industry tools is a plus, Should have a good understanding of ASIC/FPGA design flow. Also should develop a passion for writing testbench and automation scripts.
Always participate in competitions/workshops online/offline related to Design verification, It is always a good chance for you to put use of the skills you learnt to the test, If you have all these skills you have a chance in becoming a RTL design verification Engineer. and build a passion for RTL code.
Note: Skills and requirement will change according to the company, But I have mentioned everything I have researched.
4. Physical Design Engineer
Role : A Physical Design Engineer is responsible for translating the digital design into a manufacturable physical layout while ensuring various constraints are met. Their primary role is to implement Partitioning, Floor planning, Placement, Routing, Clock tree synthesis, Static timing analysis of the various blocks of the chip to ensure that the design meets timing, power, and signal integrity requirements. They work to close timing paths, reduce power consumption, and optimize area usage through iterative design and simulations. Their role begins after the chip architect and RTL design engineers have developed the RTL code and synthesized it into gate level netlist by Synthesis engineer.
They play a critical role in preparing the chip for tapeout, handling design-rule checks (DRC) and layout-versus-schematic (LVS) checks to ensure the design is ready for fabrication. Physical design stage is indeed one of the most time-consuming and critical parts of semiconductor chip design as even minor adjustments can significantly impact performance or yield. Despite advanced EDA tools, much of their work involves iterative manual fine-tuning. Even minor errors can lead to costly production issues. The complexity of physical design is often underestimated and most companies employ Physical Design verification team to check for error and run simulation for various conditions, it requires both a broad strategic view and meticulous attention to detail, making it one of the most challenging stages in chip design.
Day in the life of Physical Design Engineer :
Physical design Engineers spend most of their time working on floor planning and placement using EDA tools, perform timing analysis and routing to ensure optimal performance.
They would Participate in daily meetings to discuss progress, issues, and coordinate with other teams, focusing on discussions around timing, power, and area optimizations.
Most of Physical design Engineer time would be spend on running simulation and working around bugs in Innovus or ICC and writing TCL code to automatic something to fix a problem that shouldn't happen in the first place.
The months leading up to the Tapeout are always hectic, as last-minute issues from other teams may require them to work overtime to resolve the bugs and run the simulation.
Skills Needed :
Technical Skills : EDA Tools( Genus, Innovus, Tempus, Voltus), Physical design flow, Digital design, ASIC/SOC design and implementation, Computer Architecture, Analog/Digital circuit design, PPA tradeoff, Static timing Analysis.
Programming Languages : Verilog, SystemVerilog, Python, Perl
How to become a Physical Design Engineer : Most roles in this field demand a Master's or Ph.D in Computer Engineering, Electrical Engineering with focus on Digital design and Computer Architecture. With the necessary skills, it is entirely feasible to step into the role of an Physical design Engineer immediately after graduating but it is highly competitive job that has fewer number of openings So you have to be the best in this field to increase your chances.
Students should gain hands on projects, internships, or research labs where you can write and simulate RTL to GDSII. Learning every step of floorplanning, Pnr, STA. Also should have a decent exposure to industry EDA tools and You should work on a few projects related to Physical design to gain a better understanding of whether this is the field you want to pursue.
Always participate in competitions/workshops online/offline related to Physical design, In my next blog I will share more details about the projects/workshops needed for different roles, You can refer those projects to make even better projects using the skills you develop, It is always a good chance for you to put use of the skills you learnt to the test, If you have all these skills you have a chance in becoming a Physical Design Engineer.
Note: Skills and requirement will change according to the company, But I have mentioned everything I have researched.
Pic Courtesy : Wikipedia
5. DFT Engineer
Role : A DFT (Design-for-Test) Engineer is responsible for designs and implementation of test structures into semiconductor circuits. While Physical Design Engineers translate the logical circuit design into a physical layout ensuring the chip meets area, timing, and power constraints, DFT Engineers then incorporate testability features into the design. Their work ensures that once the chip is fabricated, it can be properly tested with automated test equipment (ATE), They are responsible for integrating scan chains, built-in self-test (BIST) structures, and other test methodologies into the chip design. DFT engineers are required before and after fabricating the chip.
Building on the test structures designed by the DFT team, there will be other teams like pre silicon validation team who tests these feature before the tapeout. DFT engineer commonly use BIST/MBIST design methodology to incorporate testing mechanisms directly into the chip so overall test time is reduced. A BIST contains a Pattern Generator that creates test patterns, using pseudo-random algorithms or predefined sequences. The Response Analyzer compresses circuit outputs into a signature to validate functionality. The Control Logic oversees the BIST process, managing test sequences and transitions between test and normal modes. DFT engineer may use TCL script for handling data, So yeah every stage of semiconductor design is complex.
Day in the life of DFT Engineer :
DFT Engineers spend most of their time working writing and reviewing scripts for scan insertion and BIST for simulation and verification to ensure that test patterns can effectively cover the design and detect potential faults.
They would Participate in daily meetings with verification and test teams to discuss issues and adapting to the constantly evolving design driven by errors and various other factors.
They develop automation scripts to improve testing time and debug the issue found during simulation and working those changes with other teams. Spend hours writing scripts and debugging the errors.
Documenting every DFT methodologies, test coverage metrics and verification processes.
Skills Needed :
Technical Skills : Digital circuit design, DFT methodologies(BIST, Fault simulation, scan insertion), EDA Tools(Mentor Graphics) , Writing scripts and debugging, DFT Architecture Selection, Computer Architecture
Programming Languages : Verilog, Python, Perl, Tcl,
How to become a DFT Engineer : Most roles in this field demand a Master's or BS in Computer Engineering, Electrical Engineering with focus on Digital design and semiconductor devices. With the necessary skills, it is entirely feasible to step into the role of an DFT Engineer immediately after graduating.
Students should engage in hands-on projects and internships focused on DFT concepts and debugging, as well as applying DFT methodologies. This is a role where you will write a lot of automation scripts and debug the issue, If you are good at this then you should consider a different role, Should have a good understanding of different DFT methodologies. Also develop a passion for scripting and debugging in order to master this role
Always participate in competitions/workshops online/offline related to DFT, It is always a good chance for you to put use of the skills you learnt to the test, If you have all these skills you have a chance in becoming a DFT Engineer. It's always beneficial to network with people who share a similar background or expertise.
Note: Skills and requirement will change according to the company, But I have mentioned everything I have researched.
6. Signoff / Tapeout Engineer
Role : A Signoff/Tapeout Engineer Engineer is responsible for verifying and finalizing the physical layout of the chip before design is sent for fabrication or as I like to call “ The last line of defense to avoid a costly error during production”. while DFT engineer integrates test structures and after pre-silicon validation engineers have verified the design's functionality. Signoff / Tapeout Engineer work is a crucial final check, before it is sent to the Fab. So this involves ensuring that the layout adheres to design rules, meets timing and power specifications, and is manufacturable. They perform detailed checks and validations (often called “signoff”) before the design is sent for fabrication.
While Signoff and Tapeout engineer role may overlap and often considered as one position in smaller companies but generally Signoff Engineer focuses on DRC/LVS, Antenna checks and meet all manufacturing requirements, Tapeout Engineer focuses on packaging the design while verifying all the design documents and generating signoff reports before sending it to the foundry, They may also act as bridge between the foundry and the engineering team.
Day in the life of Signoff / Tapeout Engineer :
Signoff / Tapeout Engineers spend most of their time reviewing and updating layout files based on feedback from DRC/LVS reports, and preparing for meetings with the design and verification teams.
They would Collaborate with colleagues to fine-tune the layout, attending design reviews, and documenting changes as they prepare the signoff reports.
Scheduling a meeting with the foundry to review the design, address any potential errors, and discuss corrective measures and ensure there are no major production level errors.
Documenting all changes, metrics and verification processes.
Skills Needed :
Technical Skills : Digital circuit design, Verifications techniques, Physical design flow, Computer architecture, ASIC/SOC design and implementation, EDA Tools
Programming Languages : Tcl, Perl, Python
How to become a Signoff / Tapeout Engineer : Most roles in this field demand a Master's or BS in Computer Engineering, Electrical Engineering with focus on Digital design and semiconductor devices. With the necessary skills, it is entirely feasible to step into the role of an DFT Engineer immediately after graduating.
Students should engage in hands-on projects and internships focused on Tapeout concepts and debugging. This is a role where you a lot of attention to detail, clear communication skills, If you are good at this then you should consider a different role also Should have a good understanding of layout design, simulation, and physical verification. Also develop a passion for scripting and debugging in order to master this role.
Always participate in competitions/workshops online/offline related to Design flow, It is always a good chance for you to put use of the skills you learnt to the test, If you have all these skills you have a chance in becoming a Signoff / Tapeout Engineer. It's always beneficial to network with people who share a similar background or expertise.
Note: Skills and requirement will change according to the company, But I have mentioned everything I have researched.
Pic courtesy : Tiny Tapeout
Additional Information : I can’t write everything I know or have researched about a role in just a few paragraphs, If explained fully it would take nearly 10 pages for each one! If you’re interested in these blogs or would like to discuss a specific position, feel free to contact me for a conversation.
There are many roles involved in the designing of these chips that I haven’t mentioned here. Explaining every role from RTL to Tapeout would make this blog around 150 pages long, which is why I plan to write a series of blogs exploring each role in detail.
Please note that the skills and the day-to-day responsibilities of an engineer I’ve mentioned are general and may vary depending on the company. I’ll leave my contact information here. If you’re interested in discussing a role or need more details about a position you couldn’t find online, feel free to reach out I’ll do my best to help. You can find similar information in Chat GPT or other LLM but the information found in this blog is from professionals who work in the industry.
If you find any mistake in this blog, Kindly send me a mail so I can verify the error and make changes accordingly.
Gmail : gbukkapa@ucsc.edu
LinkedIn : www.linkedin.com/in/gowrav-raj
Reference
Wikipedia: Utilized for broad, crowd-sourced information on semiconductor design roles, providing foundational definitions and context.
Careers Page: Consulted to obtain detailed role-specific expectations and job descriptions based on established industry standards.
Industry Professionals: Engaged with experienced professionals to gather real-world insights into day-to-day responsibilities.
Personal Experience: Incorporated practical, hands-on knowledge and industry-relevant details from my own exposure, reflecting my commitment to a career in semiconductor design.